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TMC2242C
Digital Half-Band Interpolating/Decimating Filter
12-bit In/16-bit Out, 60 MHz Features
* * * * * * * * * * * * * * Pin-compatible upgrade of TMC2242B User-selectable interpolate d.c. gain, 0 dB or -6 dB True unity d.c. gain in all "0 db" modes 40 MSPS performance in equal-rate filter modes 40 and 60 MSPS speed grades in all other modes User-selectable 2:1 decimation, 1:2 interpolation, and equal-rate filter modes, plus unfiltered bypass/delay mode Defeatable x/sin(x) compensation filter Passband ripple <0.014 dB Stopband rejection >56 dB Dedicated 12-bit two's complement or unsigned input bus 16-bit two's complement or unsigned output bus with user-selectable rounding to 8 to 16 effective bits Programmable limiter prevents overflow or clips to CCIR601 levels New double-latency modes match Y channel data flow to slower-sampled CB and CR data flows New dual-channel interpolation and decimation for YUV422
Description
The TMC2242C, a linear-phase low-pass half-band digital filter with fixed coefficients, can be used to halve or double the sampling rate of a digital signal. When used as a decimating post-filter with a double-speed oversampling A/D converter, it greatly reduces the cost and complexity of the required analog antialiasing pre-filters. When used as an interpolating pre-filter with a double-speed oversampling D/A converter, it greatly reduces the complexity and cost of the necessary analog post-filter, particularly when its x/sin(x) correction filter is engaged. The TMC2242C user selects the mode of operation (decimate, interpolate, equal-rate, bypass, x/sin(x))and rounding. The part can accept 12-bit two's complement or unsigned data at up to 60 MHz and can output saturated two's complement or offset binary data rounded to from 8 to 16 bits. Within the speed grade I/O limit, the output sample rate may be 1/2, 1, or 2 times the input sample rate. Two-channel modes permit it to interpolate or to decimate two multiplexed data streams (such as video CB and CR) jointly. The filter response is flat to within 0.014 dB up to 0.21fs (e.g. 5.75MHz at a 27MHz clock rate), with stopband attenuation greater than 56dB above 0.29fs. Symmetric-coefficient filters such as the TMC2242C always have linear phase response. Half-band response is -6 dB. Fabricated on an advanced submicron CMOS process, the TMC2242C is available in a 44-lead PLCC package. Performance is guaranteed from 0 to 70C and over a power supply range of 4.75 to 5.25V.
Applications
* Digital-to-Analog Converter Prefiltering with optional x/sinx correction * 1:2 interpolation * Analog-to-Digital Converter Postfiltering * 2:1 decimation * Low-ripple low-pass (0 to 0.2 fs) filter
Block Diagram
SI11-0 ZERO INSERT FIR FILT X/SIN(X) FILTER ROUND LIMIT DECIMATE SO15-0
SO3-0
CONTROL
65-2242C-01
DEC
INT
SYNC TCO RND
OE
Rev. 1.0.0
PRODUCT SPECIFICATION
TMC2242C
Functional Description
The TMC2242C implements a fixed-coefficient linear-phase Finite Impulse Response (FIR) filter, with special ratematching input and output structures for decimation and interpolation. For parts of each speed grade, the faster of either the input or the output bus will operate at the respective guaranteed maximum clock rate. The total internal pipeline latency from the input of an impulse to the corresponding output peak (digital group delay) is 34 clock cycles; the 39-value output response begins after 15 clock cycles and ends after 53 cycles. (The double-latency interpolation and decimation modes feature group delays of 68 clock cycles.) To interpolate, the chip accepts incoming data on alternate clock cycles, inserting zeroes on the remaining clock cycles. In decimation mode, the chip's output register is strobed at half the clock rate. In bypass and equal-rate filter modes, these input zero insertion and output register hold functions are disabled. When interpolating, the user should normally bring SYNC HIGH for at least one clock cycle, returning it LOW with the first desired input data value. The chip will then continue to accept data on alternate rising edges of CLK. The user may leave SYNC LOW or change its value once per clock cycle, with equivalent results. The chip can be powered up and operated with SYNC grounded, but the input-to-output latency may vary by 1/2 input sample period and the host system won't know which (even- or odd-numbered) CLK rising edges strobe the input register. The setup and hold timing requirements for SYNC, with respect to the rising edges of CLK, are the same as those for all other data and control inputs except OE, which is asynchronous. In two-channel mode, it must remain low after the first incoming data value. When decimating, the user should likewise bring SYNC HIGH for at least one clock cycle, returning it LOW when a fresh output is desired. The chip will continue to update the output register on alternate rising edges of CLK. The user may leave SYNC LOW or change its value once per clock cycle, with equivalent results. The chip can be powered up and operated with SYNC grounded, but the host system won't know whether the data outputs are updated on even- or odd-numbered system clock cycles. In any half-band decimating filter, a given single-cycle impulse's arrival time (on an odd versus an even clock cycle) determines whether it generates a half-amplitude two-cycle impulse or a halfspeed, 40-clock, filtered output shaped by the nonzero, noncenter coefficients. The SYNC control permits the host system to obtain consistent results. In two-channel mode, it must remain low after the first incoming data value. When the result is rounded to fewer than 16 bits, the unneeded lowest positions of the output bus are tristated and become supplementary control bits, which enable the x/sin(x) filter, bypass/delay, double-latency, dual-channel,
and other special modes. Unless more than 12 output bits are enabled, the TMC2242C offers x/sin(x) correction filtering, with or without the main low-pass filter, and without impacting the 34-cycle group delay. Bidirectional pins SO3-2 enable these modes, per Table 1. If 14 or more output bits are used, the low pass filter remains enabled, the x/sin(x), disabled.
Table 1. Operating Modes
INT 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 DEC RND2 SO3-2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Output Output Output Output 00 00 00 00 01 01 01 01 10 10 10 10 11 11 11 11 Function Interpolate (0 dB) Interpolate1 (-6 dB) Decimate Equal Rate Lowpass Interpolate (0 dB) Interpolate1 (-6 dB) Decimate Equal Rate Lowpass Interpolate (0 dB) * x/sinx Interpolate1 (-6 dB) * x/sinx Decimate * x/sinx Equal Rate LPF * x/sinx Delay + Interpolate2 (0 dB) Delay + Interpolate2 (0 dB) * x/sinx Delay + Decimate2 Bypass (Delay Only) 2-Channel Interpolate3 (0 db) 2-Channel Interpolate3 * x/sinx 2-Channel Decimate3 Delay * x/sinx
Note: 1. These modes limit to 15 bits (SO14-0) instead of 16 (SO15-0) and are provided for backward compatibility to earlier parts. 2. These modes, which double the chip's overall group delay from 34 to 68 CLK cycles, can be used to equalize intercomponent delays where Y is sampled at twice the rate of CB or CR (e.g. 4:2:2 and 8:4:4 formats). 3. These modes accommodate multiplexed two-channel data, e.g. CB/CR.
2
TMC2242C
PRODUCT SPECIFICATION
Table 2. Package Interconnections
Signal Type Timing Data In Name CLK SYNC SI11-0 Function Clock Synchronization Input Data Port PLCC Pin 42 43 40, 37-30, 27-25 4-11, 14-17 18-21 44 1 22-24 2 3 MQFP Pin 36 37 34, 31-24, 21-19 42-44, 1-5, 8-11 12-15 38 39 16-18 40 41
The output data format is two's complement if TCO is HIGH, inverted or offset binary if LOW. Unless all 16 output bits are used, the user can also select either signed or unsigned input data, via pin SO0 (see pin description note 2, below). As shown in pin description note 1, the output is half-LSB rounded to the resolution selected by the value of RND2-0. The asynchronous three-state output enable control simplifies connection to a data bus with other drivers.
Data Out SO15-4 Output Data Port
DualSO3-0 Function Controls INT DEC RND2-0 TCO OE
Output Data; Controls Interpolate Decimate Rounding Position Output Format Output Enable
Pin Assignments
SO13 SO14 SO15 OE TCO DEC INT SYNC CLK GND SI11 SO13 SO14 SO15 OE TCO DEC INT SYNC CLK GND SI11
44 43 42 41 40 39 38 37 36 35
44
43
42
41
40
6
5
4
3
2
1
18
19
20
21
22
23
24
25
26
27
28
SO12 SO11 SO10 SO9 SO8 GND VDD SO7 SO6 SO5 SO4
7 8 9 10 11 12 13 14 15 16 17
39 38 37 36 35 34 33 32 31 30 29
TMC2242C
GND VDD SI10 SI9 SI8 SI7 SI6 SI5 SI4 SI3 VDD
12
13
14
15
16
17
18
19
20
21
SO3 SO2 SO1 SO0 RND2 RND1 RND0 SI0 SI1 SI2 GND
65-2242C-02A 65-2242C-02B
44 Lead PLCC
SO3 SO2 SO1 SO0 RND2 RND1 RND0 SI0 SI1 SI2 GND
44 Lead MQFP
22
SO12 SO11 SO10 SO9 SO8 GND VDD SO7 SO6 SO5 SO4
34
1 2 3 4 5 6 7 8 9 10 11
33 32 31 30 29 28 27 26 25 24 23
TMC2242C
GND VDD SI10 SI9 SI8 SI7 SI6 SI5 SI4 SI3 VDD
3
PRODUCT SPECIFICATION
TMC2242C
Pin Descriptions
Pin Number Pin Name CLK PLCC 42 MQFP 36 Pin Function Description Clock. The chip operates from a single-phase master clock, to whose rising edges all timing parameters are referenced. All internal registers are strobed on every rising edge of CLK, although the output register is strobed on alternate rising edges during decimation. In all modes, the frequency applied to CLK is the higher of the input and output data sampling rates. During interpolation, the chip reads its input bus on alternate rising edges of CLK. Synchronization. During interpolation, the chip accepts input data on alternate rising edges of CLK and inserts zeroes on the remaining cycles. If SYNC is HIGH during CLK rising edge 0 and LOW during CLK rising edge 1, the chip will accept data on CLK 1 and insert a zero on CLK 2. Thereafter, if SYNC is either held LOW or fed a square wave of half the CLK frequency, the part will continue to accept data on odd-numbered CLK edges and to stuff zeroes on evennumbered edges. Similarly, during decimation, the output data change only on alternate clock cycles. If the user operates SYNC as above, each evennumbered rising edge of CLK will trigger a change in the output. In all other modes, the state of SYNC doesn't affect operation of the chip. Input Data. A 12-bit two's complement or unsigned input word is registered by the rising edges of CLK. SI0 is the LSB. Dedicated Timing Controls
SYNC
43
37
Dedicated Data Input Port SI11-0 40, 37-30, 27-25 4-11, 14-21 34, 31-24, 21-19 42-44, 1-5, 8-15
Dedicated Data Output Port SO15-0 Output Data MSBs. When OE is LOW, the 12 most significant bits of the filter's output emerge here, following each rising edge of CLK. The format may be two's complement, unsigned, or inverted offset binary. Bits SO15-4 correspond to input bits SI11-0, respectively. An on-chip limiter prevents overflows and underflows in the output data. Output Data. These pins serve as data outputs when RND2 is LOW. When RND2 is HIGH, they become additional filter mode controls (Table 1). Output Data 2nd LSB. This pin is a data output when RND2-1 are LOW. When either RND2 or RND1 is HIGH, it becomes an additional rounding control.1 Output Data LSB. This pin is a data output if and only if all RND bits are LOW. Otherwise, it augments the data I/O format controls.2 44, 1 2 38, 39 40 Interpolate and Decimate. Jointly with SO3-2, these bits select the chip's overall operating mode, as discussed earlier in Table 1 Output format control. When TCO is HIGH, the output data are in two's complement format. When TCO is LOW, they are inverted offset binary, unless SO0 is HIGH and RND is nonzero, in which case they are unsigned. Round and output tristate. Selects output rounding position and active bus width 8-16 bits. All outputs at and below the rounding bit position are tristated, allowing the 4 LSBs to become control inputs. Output enable. LOW activates output bus from SO15 down to the effective LSB, as chosen by RND2-0. All drivers at and below the rounding point are disabled, as are all drivers when OE is HIGH.
Dual Function Data Output/Control Input Pins SO3-2 SO1 SO0
Dedicated Static Controls (Set state before first desired data input.) INT, DEC TCO
RND2-0
22-24
16-18
Active, Asynchronous Control OE 3 41
4
PRODUCT SPECIFICATION
TMC2242C
Notes: 1. Rounding Operation Detail RND2-0 000 001 010 011 100 100 101 110 111 SO1 OutputA OutputA X X 0 1 0 1 X Output Rounding SO15-0 (16 bits) SO15-1 (15 bits) SO15-2 (14 bits) SO15-3 (13) SO15-4 (12) SO15-8 (8) SO15-5 (11) SO15-6 (10) SO15-7 (9)
2. I/O Format Operation Detail RND 0 0 >0 >0 >0 >0 SO0 Output Output 0 0 1 1 TCO 0 1 0 1 0 1 In Format 2's Comp 2's Comp 2's Comp 2's Comp Unsigned Unsigned Out Format Inverted Offset 2's Comp Inverted Offset 2's Comp Unsigned 2's Comp
A. If RND2-0 = 00X, do not drive SO1, externally.
Absolute Maximum Ratings
(beyond which the device may be damaged)1 Parameter Supply Voltage Input Voltage Output Applied Voltage2 Externally Forced Current3,4 Single output in HIGH state to ground -20 10 seconds -65 Short Circuit Duration Operating Temperature (Case) Junction Temperature Lead Soldering Temperature Storage Temperature Conditions Min -0.5 -0.5 -0.5 -3.0 Max 7.0 VDD + 0.5 VDD + 0.5 +6.0 1 110 140 300 150 Units V V V mA sec C C C C
Notes: 1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded. 2. Applied voltage must be current limited to specified range. 3. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current flowing into the device.
5
PRODUCT SPECIFICATION
TMC2242C
Operating Conditions
Conditions VDD fCLK tPWH tPWL tS tH VIH VIL IOH IOL TA Power Supply Voltage Clock frequency CLK pulse width, HIGH CLK pulse width, LOW Input Data Set-up Time Input Data Hold Time Input Voltage, Logic HIGH Input Voltage, Logic LOW Output Current, Logic HIGH Output Current, Logic LOW Ambient Temperature, Still Air 0 TMC2242C TMC2242C-1 6 6 6 0 2.0 0.8 -2.0 4.0 70 Min 4.75 Nom 5.0 Max 5.25 40 60 Units V MHz MHz ns ns ns ns V V mA mA C
Electrical Characteristics
P arameter IDD Total Power Supply Current IDDU Power Supply Current, Unloaded Power Supply Current, Quiescent I/O Pin Capacitance Input Current, HIGH Input Current, HIGH (Pulldown SO0-SO3) Input Current, LOW Leakage Current, HIGH Leakage Current, HIGH (Pulldown SO0-SO3) Leakage Current, LOW Short-Circuit Current Output Voltage, HIGH Output Voltage, LOW Conditions VDD = Max, CLOAD=25pF, fCLK=Max TMC2242C TMC2242C-1 VDD = Max, OE = HIGH, fCLK=Max TMC2242C TMC2242C-1 VDD = Max, CLK = LOW 5 VDD = Max, VIN = VDD VDD = Max, VIN = VDD VDD = Max, VIN = 0 V OE = HIGH, VOUT = VDD OE = HIGH, VOUT = VDD OE = HIGH, VOUT = 0 V VDD = Max, Output = HIGH, one pin to ground, one second duration max. SO15-0, IOH = Max SO15-0, IOL = Max 10 -10 +150 10 10 -10 +150 10 -150 Min Typ Max 150 220 135 200 5 Units mA mA mA mA mA pF A A A A A A mA V V
IDDQ CPIN IIH IIH
(PD)
IIL IOZH IOZH
(PD)
IOZL IOS VOH VOL
-90 2.4
0.4
Switching Characteristics
Parameter Output Delay Time tDO tHO Output Hold Time tENA Output Enable Time tDIS Output Disable Time Conditions CLOAD = 25 pF CLOAD = 25 pF CLOAD = 0 pF CLOAD = 0 pF Min 2.5 15 30 Typ Max 15 Units ns ns ns ns
6
PRODUCT SPECIFICATION
TMC2242C
Table 3a. Input Data Formats and Bit Weighting
Format Two's Comp. Unsigned SI11 -20 20 SI10 2-1 2-1 S9 2-2 2-2 ... ... ... SI1 2-10 2-10 S0 2-11 2-11
Table 3b. Output Data Formats and Bit Weighting
Format Two's Comp. Unsigned1 -6 dB t.c.2 -6 dB Unsgn3 SO15 -2
0
SO14 2
-1
SO13 2
-2
... ... ... ... ...
SO5 2
-10
SO4 2-11 2-11 2-10 2-10
20 -20 0
2-1 -20 20
2-2 2-1 2-1
2-10 2-9 2-9
Notes: 1. Inverted offset binary is the same as unsigned, except that all bits are complemented. 2. In -6 dB interpolation modes, the two's complement sign bit is replicated in SI15 and SI14. 3. In -6 dB interpolation mode, the unsigned MSB is preceded by a 0 in SO15. 4. A leading minus sign denotes the two's complement sign bit. 5. In all operating modes except "interpolate -6 dB," dc gain is exactly unity.
Table 4. Rounded LSBs as a function of RND2-0
RND2-0 SO15 SO15 SO15 SO15 SO15 SO15 SO15 SO15 SO14 SO14 SO14 SO14 SO14 SO14 SO14 SO14 SO13 SO13 SO13 SO13 SO13 SO13 SO13 SO13 ... ... ... ... ... ... ... ... SO8 SO8 SO8 SO8 SO8 SO8 SO8 SO8 SO7 SO7 SO7 SO7 SO7 SO7 SO7 SO7r SO6 SO6 SO6 SO6 SO6 SO6 SO6r z SO5 SO5 SO5 SO5 SO5 SO5r z z SO4 SO4 SO4 SO4 SO4r z z z SO3 SO3 SO3 SO3r z z z z SO2 SO2 SO2r z z z z z SO1 SO1r z z z z z z SO0r z z z z z z z 000 001 010 011 1002 101 110 111
Note: 1. The "r" indicates that the trailing significant output bit has been rounded to the nearest 1/2 LSB. All output drivers at and below the rounding bit are disabled, allowing the lower output bits to be used as control inputs. 2. If SO1 = 1, format is 8 bits, viz: SO15...SO8r z...z.
Table 5. Steady-State Output Values and Limit Triggers
Input Unsigned FFF C00 801 800 7FF 400 000 2's Comp. 7FF 400 001 000 FFF C00 800 Interpolate -6 dB Unsigned 7FF81 6000 4008 4000 3FF8 2000 00001 2's Comp. 3FF81 2000 0008 0000 FFF8 E000 C0001 All Other Modes Unsigned FFF01 C000 8010 8000 7FF0 4000 00001 2's Comp. 7FF01 4000 0010 0000 FFF0 C000 80001 1/4-scale zero 1/2-scale Interpretation Unsigned full-scale 3/4-scale 2's Comp. full-scale + 1/2 scale + 1 LSB + Zero 1 LSB - 1/2-scale - full-scale -
Notes: 1. Full-scale values are minima and maxima permitted by on-chip limiter. Transient overshoots arising from large input signal transitions will be clipped to these limits.
7
TMC2242C
PRODUCT SPECIFICATION
Performance Curves
0 -10 -20 Response (dB) -30 -40 -50
65-2242C-03
-60 -70 -80 0.00
0.05
0.10
0.15
0.20 0.25 0.30 Normalized Frequency
0.35
0.40
0.45
0.50
Figure 1. Frequency Response
0.030 0.025 0.020 Response (dB) 0.015 0.010 0.006
65-32242C-04
0.000 -0.008 -0.010 0.00
0.05
0.10
0.15
0.20
0.35
Normalized Frequency
Figure 2. Passband Ripple Response
110 100 90 80 %/Full Scale 70 60 50 40 30 20 10 0 -10 0 10 20 30 Sample 40 50 60
65-2242C-05
Figure 3. Step Response
8
PRODUCT SPECIFICATION
TMC2242C
Equivalent Circuits
VDD VDD
p Digital Input
p Digital Output n
n
GND
65-2242C-09
65-2242C-10
GND
Figure 4. Equivalent Digital Input Circuit
Figure 5. Equivalent Digital Output Circuit
Timing Diagrams
1/fC CLK tS SI11-0 34 35 tH 36 37 38 tPWH tPWL
SYNC tHO SO15-0 OE is LOW. 1 2 tDO 3 4
65-2242C-06
Note: Values at SO15-0 are impulse response centers (peaks) corresponding to same-numbered inputs. Figure 6. Equal Rate Mode
1/fC CLK 34 tS SI11-0 34 35 35 tH 36 37 36
tPWH 37
tPWL 38
38
SYNC tHO SO15-0 OE is LOW. 1 3
65-2242C-07
Figure 7. Decimate Mode
9
TMC2242C
PRODUCT SPECIFICATION
1/fC CLK 34 tS SI11-0 35 35 tH 37 36
tPWH 37
tPWL 38
SYNC tHO SO15-0 OE is LOW. 1 2 tDO 3 4
65-2242C-08
Figure 8. Interpolate Mode
1/fC CLK 68 tS SI11-0 68 69 69 tH 70 71 70
tPWH 71
tPWL 72
72
SYNC tHO SO15-0 OE is LOW. 1 3
65-2242C-14
Figure 9. Decimate Mode - Double Latency
1/fC CLK 68 tS SI11-0 69 69 tH 71 70
tPWH 71
tPWL 72
SYNC tHO SO15-0 OE is LOW. 1 2 tDO 3 4
65-2242C-15
Figure 10. Interpolate Mode - Double Latency
10
PRODUCT SPECIFICATION
TMC2242C
1/fC CLK 34 tS SI11-0 Y 67 C 35 tH 68 Y 69 C 36
tPWH 37
tPWL 38
70
Y
71
SYNC* tHO SO15-0 1 Y 2 C 5 Y
OE is LOW. *In two-channel modes, sync must be left low after the first data input.
65-2242C-16
Figure 11. Decimate Mode - Two-Channel
1/fC CLK 34 tS SI11-0 69 35 tH Y 71 36
tPWH 37
tPWL 38
C
SYNC* tHO SO15-0 OE is LOW. *In two-channel modes, sync must be left low after the first data input. 1 Y C tDO Y 3 C
65-2242C-17
Figure 12. Interpolate Mode - Two-Channel
tENA OE Three-State Outputs 0.5V High Impedance tDIS 0.5V 2.0V 0.8V
65-2242C-11
Figure 13. Threshold Levels for Three State Measurements
11
PRODUCT SPECIFICATION
TMC2242C
Applications Discussion
The TMC2242C is well-suited to filtering digitized composite or component NTSC or PAL video. In Figure 14, the TMC1175A 8-bit video A/D converter outputs, D7-0, are connected to the TMC2242C inputs, SI11-4, respectively. To minimize noise and any chance of electrostatic damage, inputs SI3-0 should be grounded. Controls RND2-0 are set to 100 and SO1 is forced high to effect 8-bit rounding. SO3-2, TCO, and DEC are forced low, whereas INT and SO0 are forced high. (Setting SO0 high and TCO low selects unsigned binary format at the input and output data ports, eliminating the need for external MSB inverters.)
In Figure 15, the TMC2242C drives a fast D/A converter to reconstruct analog composite video. The TMC3003 10-bit digital-to-analog converter inputs, D9-0 are connected to the TMC2242C outputs SO15-6, respectively. The TMC2242C RND2-0 controls are set to 110 for rounded 10-bit interpolation operation.
TTL Clock 27.000 MHz (D1) 28.636 MHz (NTSC D2)
2 uH Composite Video 75 Ohm 300 pF
2 uH 510 pF 300 pF VIN 75 Ohm
TMC1175A 8-bit A/D AGND D7-0
TMC2242C 8 SI11-4 SO15-8 8
65-2242C-12
27.000 MHz (D1) 28.636 MHz (NTSC D2)
13.500 MHz (D1) 14.318 MHz (NTSC D2)
Figure 12. Decimating Oversampled Video With a Low Cost 8-bit A/D
TCO = 0 RND = 100 SO(3:0) = 0011 DEC = 0 INT = 1
TTL Clock 27.000 MHz (D1) 28.636 MHz (NTSC D2) TMC2242C 12 SI11-0 SO15-6 10 TMC3003 10-bit D/A D9-0 IOUT 75 Ohm AGND 13.500 MHz (D1) 14.318 MHz (NTSC D2) 27.000 MHz (D1) 28.636 MHz (NTSC D2) 2 uH 510 pF 300 pF 2 uH 300 pF Composite Video 75 Ohm
65-2242C-13
Note: Data buses are unsigned binary. Figure 13. Interpolating Digital Video Signals before Reconstruction
TCO = 0 RND = 110 SO(3:0) = 0011 DEC = 0 INT = 0
12
TMC2242C
PRODUCT SPECIFICATION
Notes:
13
PRODUCT SPECIFICATION
TMC2242C
Mechanical Dimensions - 44-Pin PLCC Package
mbol Inches Min. .165 .090 .020 .013 .026 E1 E3 Max. .180 .120 -- .021 .032 Millimeters Min. 4.19 2.29 .51 .33 .66 Max. 4.57 3.05 -- .53 .81 3 Notes: Notes 1. All dimensions and tolerances conform to ANSI Y14.5M-1982 2. Corner and edge chamfer (J) = 45 3. Dimension D1 and E1 do not include mold protrusion. Allowable protrusion is .101" (.25mm)
/NE
.685 .695 .650 .656 .500 BSC .050 BSC .042 .056 11 44 -- .004
17.40 17.65 16.51 16.66 12.7 BSC 1.27 BSC 1.07 1.42 11 44 -- 0.10
2
E E1 J
D
D1
D3/E3 B1 e J
A1 A2 B -C- LEAD COPLANARITY
ccc C
14
TMC2242C
PRODUCT SPECIFICATION
Mechanical Dimensions - 44-Lead MQFP Package
Symbol A A1 A2 B C D/E D1/E1 e L N ND ccc Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. All dimensions and tolerances conform to ANSI Y14.5M-1982. 2. Dimensions "D1" and "E1" do not include mold protrusion. 3. Pin 1 identifier is optional. 4. Dimension N: number of terminals. 7 5. Dimension ND: Number of terminals per package edge. 6. "L" is the length of terminal for soldering to a substrate. 7. "B" includes lead finish thickness. 2 6 4 5
.077 .093 .000 .010 .077 .083 .012 .018 .005 .009 .510 .530 .390 .398 .032 BSC .026 .037 44 11 0 7 -- .004
1.95 2.35 .00 .25 1.95 2.11 .30 .46 .13 .23 12.95 13.45 9.90 10.10 .81 BSC .66 .94 44 11 0 7 -- 0.10
D D1
e
E E1
PIN 1 IDENTIFIER
C
L 0.063" Ref (1.60mm)
See Lead Detail A A2 B A1 Seating Plane Base Plane -CLEAD COPLANARITY ccc C
15
TMC2242C
PRODUCT SPECIFICATION
Ordering Information
Product Number TMC2242CR2C TMC2242CR2C1 TMC2242CKTC TMC2242CKTC1 Temperature Range 0C to 70C 0C to 70C 0C to 70C 0C to 70C Speed Grade 40 MHz 60 MHz 40 MHz 60 MHz Screening Commercial Commercial Commercial Commercial Package 44-Lead PLCC 44-Lead PLCC 44-Lead MQFP 44-Lead MQFP Package Marking 2242CR2C 2242CR2C1 2242CKTC 2242CKTC1
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com 6/1/99 0.0m 004 Stock#DS7002242C (c) 1998 Fairchild Semiconductor Corporation

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